The current state of the art in flash memory technology uses an interpoly dielectric stack typically consisting of the following layers: silicon dioxide (bottom), silicon nitride (middle), and silicon dioxide (top), known as an "ONO" (hereinafter referred to as ONO). The thickness of the ONO stack ranges from 100 .ANG. to 300 .ANG., assuming a dielectric constant of 3.7 for the entire dielectric stack. The top oxide layer of the ONO stack is typically formed by thermal growth in an ambient steam. The middle nitride layer of the ONO stack is typically thinned during the formation of the top oxide layer. The bottom oxide layer of the ONO stack is exposed to the conditions arising from the formation of these two upper layers of the ONO stack. Accordingly, the electrical integrity of the bottom oxide layer is extremely critical to device performance. The thinning action acting on the previously formed oxide or nitride layer of the ONO stack introduces a problem: unreliable thickness determination of the completed ONO stack.
While U.S. Pat. Nos. 5,166,904 and 4,758,986 disclose texture asperities and roughness on polysilicon surfaces for the purpose of creating asymmetry in the structure to affect the electron tunneling and the magnitude of the tunneling threshold voltage, to Applicants' knowledge, no known flash memory fabrication process exists for forming nor flash memory structure exists having a specially formed treatment layer as a protective layer disposed between a bottom layer of a multi-layered interpoly dielectric stack prior to formation of the complete interpoly dielectric stack. In addition, no known flash memory fabrication process exists for forming nor flash memory structure exists, having a specially formed treatment layer, described supra, which both optimizes and improves structural and electrical characteristics of the subsequently formed interpoly dielectric stack, notwithstanding any adverse thinning action introduced by the dielectric stack fabrication process. Further, no known flash memory fabrication process exists for forming nor flash memory structure exists, having a specially formed treatment layer, supra, which both improves the reliability of the bottom oxide layer of an ONO interpoly dielectric stack and facilitates decreasing pf an ONO stack thickness, thereby resulting in capacitor coupling ratio changes of the flash memory element and, therefore, allowing the use of new power supply and programming voltages.